{"id":4,"date":"2011-12-08T11:55:34","date_gmt":"2011-12-08T11:55:34","guid":{"rendered":"http:\/\/project.inria.fr\/template1\/?page_id=4"},"modified":"2021-08-30T15:49:10","modified_gmt":"2021-08-30T13:49:10","slug":"home","status":"publish","type":"page","link":"https:\/\/project.inria.fr\/coloc\/","title":{"rendered":"COLOC"},"content":{"rendered":"

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With increasing heterogeneity in both computational devices and memory organization in high performance computing platforms, movement of data between devices and layers of memory has become a critical challenge for science and engineering users of these platforms. Imminent arrival of exascale platforms has brought these concerns to the forefront.<\/div>\n
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The\u00a0objective of this workshop is to understand the impact of abstractions and tools that have been around for some time and have seen some adoption.<\/div>\n
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Location<\/strong><\/h5>\n
COLOC is a joint workshop of\u00a0EuroPar 2021<\/a>.<\/div>\n
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Schedule<\/strong><\/h5>\n

2:20pm CEST\/ 7:20am CDT – Introduction<\/p>\n

Keynote 1 :\u00a0Torsten Hoefler,\u00a0Professor, Department of Computer Science, ETH Zurich<\/span><\/strong><\/p>\n

2:30pm CEST\/7:30am CDT –\u00a0 Data-Centric Python – Productivity, portability and all with high performance!<\/p>\n

 <\/p>\n

3:00pm CEST\/8:00am CDT –\u00a0\u00a0Locality-Aware Scheduling of Independent Tasks for Runtime System<\/span><\/p>\n

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3:30pm CEST\/8:30am CDT –\u00a0High Performance Computing with Java Streams<\/span><\/p>\n

4:00pm CEST\/9:00 am CDT – Break<\/p>\n

4:15pm CEST\/9:15am CDT –\u00a0Exploring Strategies to Improve Locality Across Many-core Affinities<\/span><\/p>\n

4:40pm CEST\/9:40am CDT –\u00a0Monitoring Collective Communication Among GPUs<\/span><\/p>\n

 <\/p>\n

Keynote 2 : William E. Hart — Data Anal. and Opt. Lead, The Exascale Computing Project\u00a0<\/strong>5:05pm CEST\/10:00am CDT – ECP: Data Analytics and Optimization Applications On Accelerator-Based Systems<\/p>\n

 <\/p>\n

5:40pm CEST\/10:40am CDT – Panel<\/p>\n

 <\/p>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n

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Call for papers\u00a0: <\/strong>https:\/\/project.inria.fr\/coloc\/call-for-papers\/<\/strong><\/a><\/h6>\n

 <\/p>\n<\/div>\n

 <\/p>","protected":false},"excerpt":{"rendered":"

With increasing heterogeneity in both computational devices and memory organization in high performance computing platforms, movement of data between devices and layers of memory has become a critical challenge for science and engineering users of these platforms. Imminent arrival of exascale platforms has brought these concerns to the forefront. The\u00a0objective\u2026<\/p>\n

Continue reading<\/span><\/i><\/a> <\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"open","template":"templates\/template-onecolumn.php","meta":{"footnotes":""},"class_list":["post-4","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/project.inria.fr\/coloc\/wp-json\/wp\/v2\/pages\/4","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/project.inria.fr\/coloc\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/project.inria.fr\/coloc\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/project.inria.fr\/coloc\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/project.inria.fr\/coloc\/wp-json\/wp\/v2\/comments?post=4"}],"version-history":[{"count":64,"href":"https:\/\/project.inria.fr\/coloc\/wp-json\/wp\/v2\/pages\/4\/revisions"}],"predecessor-version":[{"id":214,"href":"https:\/\/project.inria.fr\/coloc\/wp-json\/wp\/v2\/pages\/4\/revisions\/214"}],"wp:attachment":[{"href":"https:\/\/project.inria.fr\/coloc\/wp-json\/wp\/v2\/media?parent=4"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}