The safety-critical embedded industries, such as avionics, automobile, robotics and health-care, require guarantees for hard real-time and correct application execution. As applications are becoming more complex, their computational demands scale rapidly, requiring architectures with multiple processing elements. Although multicore architectures can effectively satisfy the needs of best-effort systems, the same cannot be stated for critical embedded systems for two main reasons: hard-to-predict timing behaviour and increased fault susceptibility.
Hard-to-predict timing behaviour originates from the complex nature of modern systems. Not only the application complexity, but also the hardware complexity has been increased. To improve average performance, modern architectures have been enhanced with dynamic hardware components, which, however, have variable timing behaviour, e.g., cache memories and branch predictors. Parallel execution of applications on the same platform leads to concurrent accesses to shared resources, e.g., memory hierarchy and communication means. These concurrent accesses introduce timing delays (interferences), highly affecting applications’ timing behaviour. To provide hard real-time guarantees, safe, but pessimistic, Worst-Case Execution Time (WCET) estimations have to be employed during system design.
Increased fault susceptibility stems from the very nature of electronic systems. Reliability threats, such as manufacturing process variation, aging and soft errors, depend on transistors size and are expected to significantly increase with transistors shrinking. The most important reliability threats have been considered soft errors occurring due to environmental conditions, e.g., high temperature and high-energy electromagnetic radiation. However, with the further ongoing reduction of transistors size, faults will occur even under normal operation conditions, which was not the case with technology used a decade ago. Due to this unreliable nature of electronic systems, the susceptibility of multicore architectures towards reliability threats is inevitable.
The goal of FASY is to tackle the combined challenge of designing time-predictable and reliable multicore embedded systems. FASY will provide the means to analyse both functional and timing behaviour of applications executed on multicore architectures, perform fault-aware WCET estimation and design cores with time-predictable and reliable execution, under faults. This will be achieved through novel approaches considering both reliability and WCET aspects. FASY will be based on open-source cores, providing flexibility and removing the limitations of COTS platforms.
