International Conferences
- A. Kritikakou, P. Nikolaou, I. Rodriguez-Ferrandez, J. Paturel, L. Kosmidis, M.K. Michael, O. Sentieys, D. Steenari, “Functional and Timing Implications of Transient Faults in Critical Systems”, IEEE International Symposium on On Line Testing and Robust System Design (IOLTS), 2022
- F.F. dos Santos, A. Kritikakou, and O. Sentieys, “Experimental evaluation of neutron-induced errors on a multicore RISC-V platform”, IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), 2022
- Pegdwende Romaric Nikiema, Alessandro Palumbo, Allan Aasma, Luca Cassano, Angeliki Kritikakou, Ari Kulmala, Jari Lukkarila, Marco Ottavi, Rafail Psiakis, and Marcello Traiola, “Towards Dependable RISC-V Cores for Edge Computing Devices“, IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), 2023
- Pegdwende Romaric Nikiema, Angeliki Kritikakou, Marcello Traiola, and Olivier Sentieys, “Design with low complexity fine-grained Dual Core Lock-Step (DCLS) RISC-V processors“, IEEE/IFIP International Conference on Dependable Systems and Networks – Supplemental Volume (DSN-S), 2023
- Pegdwende Romaric Nikiema, Angeliki Kritikakou, Marcello Traiola, and Olivier Sentieys, “Impact of transient faults on timing behavior and mitigation with near-zero WCET overhead“, Euromicro Conference on Real-Time Systems (ECRTS), 2023
- Pegdwende Romaric Nikiema, Marcello Traiola, and Angeliki Kritikakou, “Special Session: Impact of Compiler Optimizations on the Reliability of a RISC-V-based Core“, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2024
- Pegdwende Romaric Nikiema, Marcello Traiola, and Angeliki Kritikakou, “Special Session: Impact of Compiler Optimizations on the Reliability of a RISC-V-based Core“, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2024.
Workshop
- Pegdwende Romaric Nikiema, Angeliki Kritikakou, Marcello Traiola, and Olivier Sentiey, “Design with low complexity fine-grained Dual Core Lock-Step (DCLS) RISC-V processors“, IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE), 2023. Note: Best paper award, included in the proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks (DSN) 2023.
Posters
- F.F. dos Santos, A. Kritikakou, and O. Sentieys, “Experimental Evaluation of Neutron Induced Errors on a RISC V Processor”, Spring RISC-V week, 2022
- Angeliki Kritikakou, Pegdwende Romaric Nikiema, Marcello Traiola, and Olivier Sentieys, “Time-Bounded Error Mitigation through Dual-Core Lockstep RISC-V using HLS”, RISC-V Summit Europe, 2023
