1st RISC-V 128-bit Workshop@RISC-V Summit Europe 2024

The ever growing memory needs in computer infrastructures make 128-bit addresses a possible long-term solution to access vast swaths of data uniformly. However the way software and hardware of future machines could exploit such a vast address space are open questions.

RISC-V and its 128-bit variant (RV-128) provide an opportunity to unify all the components of large machines, rack-sized and beyond. This should enable all the machine’s processors, CPUs and accelerators alike, to share a minimum common instruction set. Furthermore, 128-bit virtual addresses could provide a unified view of the machine at the process level, while 128-bit physical addresses organize all the machine’s memory into a single, physically distributed address space. The benefits would be easier management of heterogeneity and disaggregation, and a means towards a unified software view of the machine.

There are many open questions, including:

  • What classes of applications could benefit from a machine-wide 128-bit address space?
  • How can we organize remote access, or the migration of code or data from one node to another?
  • What would be the properties of a machine-wide virtual 128-bit address space? How should we organize its consistency and distribution?
  • How should we set up a practical machine-wide physical address space?
  • What would be the scope of an operating system’s kernel mode on such a machine? How would it interface with a machine-wide user mode distributed process?
  • What would be the programming models for unified but distributed applications?

The goal of this workshop is to expand and refine the list of open questions, identify research directions and help enabling an active RISC-V 128-bit community.

This 1st RISC-V 128-bit European Workshop will take place on June 28th in Munich (Germany), as a side-event of the RISC-V Summit Europe. Participation to the workshop requires to opt in for “Friday Side Events” during registration, and pay the associated fee.

The program is under construction, and will be posted here soon.

The Workshop is partially funded by the French ANR project Maplurinum (Grant n°ANR-21-CE25-0016). Its Program Committee is composed of:

  • Mathieu Bacou (Télécom SudParis, INRIA Saclay).
  • Christian Fabre (CEA LIST, Grenoble).
  • César Fuget (CEA LIST, Grenoble).
  • Pierre Michaud (INRIA Rennes).
  • Arthur Perais (CNRS, Grenoble INP TIMA Lab, Grenoble).
  • Frédéric Pétrot (Grenoble INP TIMA Lab, Grenoble).
  • Gaël Thomas (INRIA Saclay).


  1. “128-bit addresses for the masses (of memory and devices)”. HotInfra 2023 workshop, at ISCA 2023. https://cea.hal.science/DSCIN/cea-04487782v1

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