Mourad HAFIDI, PhD Thesis, “GPS on stochastic architecture”, Université de Bretagne Sud, Novembre 2018. Available on line
 M. M. Hafidhi and E. Boutillon, “Improving the Performance of the Carrier Tracking Loop for GPS Receivers in Presence of Transient Errors due to PVT Variations,” 2016 IEEE International Workshop on Signal Processing Systems (SiPS), Dallas, TX, 2016, pp. 80-85.doi: 10.1109/SiPS.2016.22 https://hal.archives-ouvertes.fr/hal-01391201v1
 M. M. Hafidhi, E. Boutillon and C. Winstead, “Reducing the impact of internal upsets inside the correlation process in GPS Receivers,” 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP), Krakow, 2015, pp. 1-5. doi: 10.1109/DASIP.2015.7367264 https://hal.archives-ouvertes.fr/hal-01211180v1
 M. M. Hafidhi and E. Boutillon, “Hardware error correction using local syndromes,” 2017 IEEE International Workshop on Signal Processing Systems (SiPS), Lorient, 2017, pp. 1-6. doi: 10.1109/SiPS.2017.8109995 https://hal.archives-ouvertes.fr/hal-01611117v1
 M. Dridi, M. M. Hafidhi, C. Winstead and E. Boutillon, “Reliable NCO carrier generators for GPS receivers,” 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP), Krakow, 2015, pp. 1-5. doi: 10.1109/DASIP.2015.7367266 https://hal.archives-ouvertes.fr/hal-01211192v1
 M. M. Hafidhi, E. Boutillon and C. Winstead, “Reliable gold code generators for GPS receivers,” 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, CO, 2015, pp. 1-4. doi: 10.1109/MWSCAS.2015.7282164 https://hal.archives-ouvertes.fr/hal-01151895v1
 I. Wali, E. Casseau, A. Tisserand, “An Efﬁcient Framework for Design and Assessment of Arithmetic Operators with Reduced-Precision Redundancy”, Conference on Design and Architectures for Signal and Image Processing (DASIP), Dresden, Germany, pp.1-6, September 27-29, 2017. https://ieeexplore.ieee.org/document/8122117
 P. Dobias, E. Casseau, O. Sinnen, “Comparison of Different Methods Making Use of Backup Copies for Fault-Tolerant Scheduling on Embedded Multiprocessor Systems”, Conference on Design and Architectures for Signal and Image Processing (DASIP), Porto, Portugal, pp.1-6, October 10-12, 2018. https://ieeexplore.ieee.org/document/8597044
 P. Dobias, E. Casseau, O. Sinnen, “Restricted Scheduling Windows for Dynamic Fault-Tolerant Primary/Backup Approach-Based Scheduling on Embedded Systems”, SCOPES ’18: 21th International Workshop on Software and Compilers for Embedded Systems, Sankt Goar, Germany, May 28-30, 2018. https://dl.acm.org/citation.cfm?doid=3207719.3207724
 Nasser, Y., Prevotet, J. C., & Hélard, M. (2018, May). Power modeling on FPGA: a neural model for RT-level power estimation. In Proceedings of the 15th ACM International Conference on Computing Frontiers (pp. 309-313). ACM.
 Sara Zermani, Catherine Dezan, Chabha Hireche, Reinhardt Euler, and Jean-Philippe Diguet. Embedded and Probabilistic Health Management for the GPS of Autonomous Vehicles. In 5th Mediterranean Conference on Embedded computing, Bar, Montenegro, June 2016.(MECO Award of “Gratitude for contribution in scientific and research work”)
 Sara Zermani, Catherine Dezan, Chabha Hireche, Reinhardt Euler, and Jean-Philippe Diguet. Embedded Context aware Diagnosis for a UAV SoC platform. Microprocessors and Microsystems : Embedded Hardware Design (MICPRO), 51 :185–197, June 2017
 M. M. Hafidhi, E. Boutillon and A. Dion, “Demo: Localisation in a faulty digital GPS receiver,” 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), Rennes, 2016, pp. 223-224. doi: 10.1109/DASIP.2016.7853824
 Mohamed Hafidhi, Emmanuel Boutillon, “Reliable GPS position on an unreliable hardware”, poster, GDR SOCSIP, June 2016, Nantes, France. 〈https://colloque-socsip.ietr.fr/#page=home〉
 General audience presentation video of CominLab’s RELIASIC project, 2016 (in French):
 Lab-STICC news about the tape-out of the ASIC circuit: https://www.labsticc.fr/en/news/1187-cominlabs-reliasic-a-new-circuit-sent-to-foundry.htm.