Presentation

RIDIM: Reconfigurable stream dataflow computing near memory

Finding the ideal meeting point between software models and hardware implementations is a recurring issue since the early days of computer engineering. The software community can provide nice abstractions and formalisms that are not suited for hardware implementation. On the other side, the hardware community can provide very efficient and dedicated hardware components that are difficult to efficiently program because of a shallow abstraction model. The good-old combination between the processor and Von Neumann architecture with the imperative programming model is smashing into pieces because of memory reasons and energy efficiency drops, especially for machine learning applications. This project aims to tackle both problems and finally propose a new holistic software/hardware model by integrating processing capabilities all along the path from the main memory to the processor. The newly integrated reconfigurable components will be relevantly used thanks to a recently-developed model of computation called the passive-active flow graph.

Context

Through the numerous hardware solutions implemented from generation to generation, more and more transistors in a circuit are allocated for the sole purpose of improving memory access. In many cases, more than 80% of the area of a chip is dedicated to caches, memories and memory controllers, interconnects, etc., whose sole purpose is to store/transfer data or control the storage/transfer of data. Memory accesses are more expensive than an arithmetic operation. As a result, the total energy spent for moving data has reached excessive proportions. In a mobile system, memory aspects alone can consume up to 62% of the energy. Assigning a processor to compute a low number of very simple and basic operations is extremely inefficient from an energy point of view.

Objectives

The main objectives is to explore new architectural organizations to reduce the data movements to eventually decrease the energy consumption of computing devices.

Proposed Approach

In order to reach our goals, several separate steps have been identified. We studied and measure the data roundtrip. Two main directions are now explored:
  1. Optimization of data movements between chips
  2. Optimization of data movements inside the computing chip

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