RIDIM: Reconfigurable stream dataflow computing near memory

Finding the ideal meeting point between software models and hardware implementations is a recurring issue since the early days of computer engineering. The software community can provide nice abstractions and formalisms that are not suited for hardware implementation. On the other side, the hardware community can provide very efficient and dedicated hardware components that are difficult to efficiently program because of a shallow abstraction model. The good-old combination between the processor and Von Neumann architecture with the imperative programming model is smashing into pieces because of memory reasons and energy efficiency drops, especially for machine learning applications. This project aims to tackle both problems and finally propose a new holistic software/hardware model by integrating processing capabilities all along the path from the main memory to the processor. The newly integrated reconfigurable components will be relevantly used thanks to a recently-developed model of computation called the passive-active flow graph.

Proposed Approach

Our architectural proposition is to embed some computing capabilities all along the path between the main memory and the processor. This means integrating compute power inside the routers of the network-on-chip or inside the DRAM controller.

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