Hardware and Arithmetic for Hyperelliptic Curves Cryptography

October 2014 – December 2017

Consortium and Funding


Efficient and robust public key cryptography, or asymmetric cryptography, is of major importance for security and privacy in many applications such as communications, e-commerce, control access, cloud computing, smart-phones, body area networks, TV boxes, Internet of Things, etc. In the past, RSA was the predominant solution for asymmetric cryptography. Since a few years, elliptic curves cryptography (ECC) is now the main standard with more efficient and less power consuming implementations than RSA for a similar theoretical security level. Recent theoretical results show that hyperelliptic curve cryptography (HECC) is supposed to be a more efficient solution (on theoretical evaluations and a few software implementations) due to use of smaller finite fields elements (about half the size of ECC). Efficient arithmetic is one of the main  element for hardware implementations of HECC systems. Arithmetic plays an important in providing algorithms and number representations robust against physical attacks (e.g. analysis of the power consumption, electromagnetic radiations or computation timings). Only a very few hardware implementations of HECC (without any open source availability) are reported in the literature (and results published the last decade have too small security levels).


In this project, we study and prototype efficient arithmetic algorithms for hyperelliptic curve cryptography for hardware implementations (on FPGA circuits). We study new advanced arithmetic algorithms and representations of numbers for efficient and secure implementations of HECC in hardware. We develop efficient and secure arithmetic units in hardware for HECC (distributed as open source hardware code). We also design a fast and secure hardware implementation of HECC based on Kummer surfaces. To the best of our knowledge, there is neither similar units nor crypto-processor freely accessible for HECC implementation currently. We hope providing open source hardware code will help us to launch academic and industrial collaborations in the future. Another objective is the evaluation of trade-offs between performances (speed, internal code size, silicon cost and energy) and security (robustness against passive and active attacks). Those results may be used to guide designers during the specification of security applications (for future academic and industrial collaborations). Finally, we will perform a security evaluation against some physical attacks (side channel attacks).


Public key cryptography, cyber-security, side channel attacks, arithmetic algorithm, representations of numbers, protection, countermeasure, hardware implementation, integrated circuit, FPGA.

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