The ever growing memory needs in computer infrastructures make 128-bit addresses a possible long-term solution to access vast swaths of data uniformly. However the way software and hardware of future machines could exploit such a vast address space are open questions.
RISC-V and its 128-bit variant (RV-128) provide an opportunity to unify all the components of large machines, rack-sized and beyond. This should enable all the machine’s processors, CPUs and accelerators alike, to share a minimum common instruction set. Furthermore, 128-bit virtual addresses could provide a unified view of the machine at the process level, while 128-bit physical addresses organize all the machine’s memory into a single, physically distributed address space. The benefits would be easier management of heterogeneity and disaggregation, and a means towards a unified software view of the machine.
There are many open questions, including:
- What classes of applications could benefit from a machine-wide 128-bit address space?
- How can we organize remote access, or the migration of code or data from one node to another?
- What would be the properties of a machine-wide virtual 128-bit address space? How should we organize its consistency and distribution?
- How should we set up a practical machine-wide physical address space?
- What would be the scope of an operating system’s kernel mode on such a machine? How would it interface with a machine-wide user mode distributed process?
- What would be the programming models for unified but distributed applications?
The goal of this workshop is to expand and refine the list of open questions, identify research directions and help enabling an active RISC-V 128-bit community.
This 1st RISC-V 128-bit European Workshop will take place on January 22th in Barcelona (Spain), as a side-event of Hipeac 2025. Participation to the workshop requires to opt in for “Friday Side Events” during registration, and pay the associated fee.
The Workshop is partially funded by the French ANR project Maplurinum (Grant n°ANR-21-CE25-0016). Its Program Committee is composed of:
Program
- 10:00-10:30 – Intro & Some Recent Work on 128-bit (Workshop organizers). Slides
- 10:30-11:00 – “Virtual Memory for Post-Moore Servers”, Babak Falsafi (EPFL). Slides
- 11:30-12:00 – “128-bit RISC-V proposal: implications on HPC applications, data-center working sets, and object-oriented computing”, Osman Unsal (BSC). Slides
- 12:00-13:00 – “Directions for future large scale systems”, Daniel Hagimont (IRIT). Slides
- 13:00-14:00 – Lunch
- 14:00-14:30 – “ZETABYTE HPC Systems for 2025 and Beyond – SV/128 – RISC-V”, Steve Wallach (Guest Scientist LANL, advisor BSC), remote. Slides
- 14:30-15:30 – Panel “RISC-V 128 bit for HPC: what are the main roadblocks and opportunities for software? “: Babak Falsafi (EPFL), Alain Tchana (LIG), Daniel Hagimont (IRIT), Marc Duranton (CEA), Osman Unsal (BSC), moderator Christian Fabre (CEA)
- 15:30-16:00 – Coffee break
- 16:00-16:10 – Outro, Christian Fabre (CEA)
Detailed Program
10:00-10:30 – Intro & Some Recent Work on 128-bit (Workshop organizers)
What could be a future 128 bit HPC machine, and what does it means for software? Some remarks from the ANR project Maplurinum project:
- “Some ideas about the base software stack for future 128 bit HPC machines with > 100 M cores.” Christian Fabre (CEA LIST, Grenoble).
- “*A Short Overview of Preliminary results of Maplurinum: Microarchitectural tricks to support 128-bit RISC-V without “128-bit everywhere” and SoC integration and hardware-software interface to efficiently support 128-bit address spaces” Arthur Perais, (TIMA/CNRS, Grenoble), Cesar Fuguet (TIMA/Inria, Grenoble)
Abstract: Doubling register and datapaths will incur area, power and latency cost. A more efficient 128-bit microarchitecture is possible and will be covered. Some requirements for efficiently supporting 128-bit address spaces in a SoC will also be introduced.
Bios:
- Christian Fabre received his engineering degree from ENSIMAG, Grenoble, in 1990, with a major in « Architecture & Parallelism. » Since then he has worked in software R&D. First at the Open Software Foundation Research Institute, a non profit foundation that developed distributed systems, compilation technology, tools and kernels for Unix and open systems. Then for Groupe Silicomp (now ORANGE Business Services) on object modelling of embedded systems. He joined CEA in 2009 to work on low level software support R&D for advanced chips. Christian is very enthusiast about RISC-V, as the counterpart of open system in the hardware space. Since 2018, he has been instrumental in the organisation of several European events dedicated to RISC-V and open hardware.
- Arthur Perais has been a CNRS associate researcher at TIMA since 2020. He obtained his PhD from Université de Rennes 1 in 2015, then worked in the product team of Qualcomm Datacenter Techonlogy and Microsoft between 2016 and 2020. He focuses on general purpose core microarchitecture.
- Cesar Fuguet has been Inria associate researcher at TIMA since November 2024. He obtained his diploma in Systems Engineering from the Los Andes University in Venezuela in 2011, his Master in Computer Science from Paris 6 University in 2012, and his PhD in Computer Science and Electronics from Paris 6 University in 2015, working on coherent shared memory manycores. He worked for 9 years at CEA Leti and CEA List on coherent shared memory manycore design using 2.5D integration and on an accelerator for variable precision computing, as well as a suitable memory hierarchy for these devices. He currently focuses on RISC-V processors with 128-bit address space and heterogeneous architectures build using chiplets (2.5D and 3D).
10:30-11:00 – “Virtual Memory for Post-Moore Servers”, Babak Falsafi (EPFL)
Bio: Babak is a Professor in the School of Computer and Communication Sciences and the founder of EcoCloud, an industrial/academic consortium at EPFL investigating sustainable information technology. He is also the founding President of the Swiss Datacenter Efficiency Association with a platform and a label to quantify and certify energy efficiency and emissions in datacenter operation. He has made numerous contributions to server architecture since the 90s. His recent work on cloud-native CPUs laid the foundation for the first generation of Cavium ARM server CPUs, ThunderX. He is a recipient of an Alfred P. Sloan Research Fellowship, and a fellow of ACM and IEEE.
11:00-11:30 – Coffee break
11:30-12:00 – “128-bit RISC-V proposal: implications on HPC applications, data-center working sets, and object-oriented computing”, Osman Unsal (BSC)
Abstract: The RISC-V RV128 proposal provides an opportunity for computing to get closer – although not asymptotically – to the ideal Turing Machine. In practical terms, the proposal has implications on HPC applications in terms of going beyond double-precision floating-point, on data-center working sets in terms of page translation reach and on hardware-support for object-oriented computing. The talk will discuss these topics in the context of the RV128 proposal focusing on hardware-support for HPC and data-center applications.
Bio: Osman S. Unsal co-manages the Computer Architecture for Parallel Paradigms research group at BSC. He holds BS, MS, and Ph.D. degrees in electrical and computer engineering from Istanbul Technical University, Brown University, and the University of Massachusetts, Amherst, respectively. His current research interests include computer architecture, reliability / fault-tolerance, vector processors, and ensuring programmer productivity. Before BSC, he worked at Intel Microprocessor Research Labs; and he co-managed the BSC-Microsoft Research Center while at BSC. He was the technical leader for four European research projects and is currently technical coordinator of the DARE project.
12:30-13:00 – “Directions for future large scale systems”, Daniel Hagimont (IRIT) & Alain Tchana (LIG)
Abstract: This presentation provides an overview of the developments in parallel and distributed hardware infrastructures and systems designed to manage such infrastructures. The aim is to highlight possible directions for the design of future systems relying on such infrastructures..
Bio: Daniel Hagimont is a Professor at the National Polytechnic Institute of Toulouse and a member of the IRIT laboratory (Institute for Research in Computer Science of Toulouse), where he leads a research group focused on operating systems, distributed systems, and middleware. After graduating from the ENSIMAG engineering school (Grenoble) in 1990, he obtained a PhD from the National Polytechnic Institute of Grenoble in 1993. After a postdoctoral stay at the University of British Columbia (Vancouver, Canada) in 1993-1994, he was recruited as a researcher at INRIA Grenoble in 1994. He obtained his Habilitation to Supervise Research from the National Polytechnic Institute of Grenoble in 1998. He became a Professor at Toulouse in 2005. Daniel Hagimont has published more than 120 articles in his field of research and has supervised over 25 completed PhD thesis. He received the Senior researcher award for 2024 from the CNRS GDR RSD.
Bio: Alain Tchana is from Nkongsamba, a city in Cameroon. He is gratuated from University of Yaoundé I in 2008. Then he received his PhD in computer science in 2011 at Toulouse INP. Since September 2022 he is Professor at Grenoble INP in France. Before Grenoble, Alain Tchana was Assistant Professor at Toulouse INP (2013-2018), Professor at Nice University (2018-2019), and Professor at ENS Lyon (2019-2022). His main research interests are Virtualization and Operating Systems. Simply, Alain Tchana is a Systems guy! He has published more than 60 research papers in major Systems, Middleware, Network, and Security conferences including EuroSys, USENIX ATC, INFOCOM, VEE, Middleware, RAID, and DSN. He has also served as PC member in several conferences including USENIX ATC, EuroSys, NSDI, and DSN. Alain Tchana has co-supervised seven PhD students, five of whom are pursuing their career in academia. He has received two major prizes: the CNRS GDR RSD best junior researcher awards for 2021 in France, and the 2021 Prix de la Francophonie pour Jeunes chercheurs.
13:00-14:00 – Lunch
14:00-14:30 – “ZETABYTE HPC Systems for 2025 and Beyond – SV/128 – RISC-V”, Steve Wallach (Guest Scientist LANL, advisor BSC), remote.
Abstract: In the previous 60 years or so, significant advances in computer architecture have begun with changes to the virtual address space. The major focus was referencing more memory. Now we are dealing with heterogenous computing encompassing 100,000 of nodes, different ISA’s, personal computers, world-wide access, security issues. and open source computer architecture. SV/128 proposes to integrate these systems in a global network with extensive security features.
Bio: He is currently a guest scientist at Los Alamos National Laboratory and advisor BSC, Previously, he was Director System Arch at Micron. Micron acquired Convey Computers where he was Chief Scientist and co-founder. He was co-founder of Convex Computers, their chief technology officer and senior V.P. of development. After Hewlett-Packard bought Convex, Wallach became the chief technology officer of the large systems group. He was also a visiting professor at Rice University 1998-1999. Prior to Convex, he was manager of Advanced Development for Data General. His efforts on the MV/8000 are chronicled in “The Soul of a New Machine”.
14:30-15:30 – Panel “RISC-V 128 bit for HPC: what are the main roadblocks and opportunities for software? “: Babak Falsafi (EPFL), Alain Tchana (LIG), Daniel Hagimont (IRIT), Marc Duranton (CEA), Osman Unsal (BSC), moderator Christian Fabre (CEA).
15:30-16:00 – Coffee break
16:00-16:10 – Outro, Christian Fabre (CEA)
Abstract: Some remarks and preliminary conclusions about the workshop.
Organization
- Mathieu Bacou (Télécom SudParis, INRIA Saclay).
- Christian Fabre (CEA LIST, Grenoble).
- César Fuget (CEA LIST, Grenoble).
- Pierre Michaud (INRIA Rennes).
- Arthur Perais (CNRS, Grenoble INP TIMA Lab, Grenoble).
- Frédéric Pétrot (Grenoble INP TIMA Lab, Grenoble).
- Gaël Thomas (INRIA Saclay).
Ref:
- “128-bit addresses for the masses (of memory and devices)”. HotInfra 2023 workshop, at ISCA 2023. https://cea.hal.science/DSCIN/cea-04487782v1
