Rajesh Gupta, Inria International Chair from UC San Diego, gave two talks at the Inria Rennes Research Center

Professor Gupta’s research interests span topics in embedded and cyber-physical systems with a focus on energy efficiency from algorithms, devices to systems that scale from IC chips, and data centers to built environments such as commercial buildings. He currently leads NSF project MetroInsight with the goal to organize and use city-scale sensing data for improved services. His past contributions include SystemC modeling and SPARK parallelizing high-level synthesis, both of which have been incorporated into industrial practice. Earlier, Gupta led NSF Expeditions on Variability, and DARPA-sponsored efforts under the Data Intensive Systems (DIS) and Circuit Realization at Faster Timescales (CRAFT) programs. Gupta and his students have received a best demonstration paper award at ACM BuildSys’16 , best paper award at IEEE/ACM DCOSS’08 and a best demonstration award at IEEE/ACM IPSN/SPOTS’05. Rajesh holds an Inria International Chair since 2017 to spend  12 months at Inria over a period of 5 years and is the co-leader of the Inria@SiliconValley associate team COMPOSITE with Inria team TEA in Rennes.

Early September Rajesh gave two talks at Inria Rennes :

  • Talk on “CERTUS: *Compositional* Synthesis for High-level Design of System-Chips”

Despite extraordinary rise in capabilities due to Moore’s law, design of semiconductor chips is increasingly out of reach for most academic institutions, and even companies except for a handful. The reason is the extraordinary cost and time to design. There are fundamental reasons for this rapid escalation of design costs. This talk posited an alternate universe of design and verification that based on identification of regularity and composition of blocks that are reused from one design to another. There are serious fundamental challenges related to how chip-blocks are modeled and what can be done to make them truly composable. In this talk, Rajesh Gupta provided an overview of their efforts in this area, including experience from our most recent design of a 500-core binarized neural network accelerator in TSMC 16nm process.

  • Talk on “Building Computing Machines That Sense, Adapt and Approximate”

This talk explored a computing universe where sensing of the ongoing computation, its physical environment provides important data to adjust software/computation at different levels. The NSF Expeditions in Computing program on Variability has sought to characterize variability, program structuring and task scheduling that can make a software stack robust against variations in the computing environment. They discussed results and promising directions for continuing research in the emerging area of approximate computing.